This invention relates to multilevel converters and more specifically to a system and method for DC link voltage balancing in multilevel converters.
Multilevel converters are generally used in high power industrial applications such as variable speed drive (VSD) systems or in energy conversion applications such as a solar (or photovoltaic) power generation systems, wind turbine generators and marine and hydrokinetic power generation systems. One example of a multi-level converter is a neutral point clamped (NPC) converter. A three level converter, for example, typically includes two capacitor voltages in series with a center tap as the neutral and two phase legs each comprising two pairs of switching devices in series. In one embodiment, each switching device comprises an anti-parallel connection of a unidirectional electronic switching device, such as an insulated gate bipolar transistor or an insulated gate commutated thyristor, and a diode, such as a free-wheeling diode.
DC link voltage balancing is a challenge when operating three level neutral clamped converters (NPC). DC link voltage unbalance may overstress the capacitors and switching devices and cause over voltage and under voltage trips during the operation of the converter. In severe DC link voltage unbalance conditions, one capacitor may become fully charged to the full DC-link voltage such that stress on the capacitor and the switching devices is doubled and the output waveforms become two level rather than three-level. DC link voltage unbalance also causes an increase in output voltage total harmonic distortion (THD) and may cause the control loop to become unstable.
One of the methods of compensating DC link voltage unbalance is utilizing measured DC-link voltages for pulse width modulation (PWM) control of the three level converter. This method, however, includes additional expense, does not compensate for steady-error in DC link voltage, and also results in high THD in the output voltage and injects active 2nd harmonic current at AC side. Another method of compensating DC link voltage unbalance is to use zero sequence voltage or DC bias voltage injection. However, this method also has high THD in the output voltage at some operation points and becomes unstable at low power factors.
Therefore, it is desirable to provide a method and a system that will address the foregoing issues.